Bose-Chaudhuri-Hocquenghem (BCH) coding based on chip communication network is proposed to achieve low latency , high throughput and optimal Energy- Performabilty trade-off. The proposed encoding and decoding scheme is applied to SOC architecture as a practical example. The proposed design improves error correction as compared to conventional schemes. The throughput of Butterfly fat tree(BFT)/BCH architecture is increased by 50%. The design decreases the latency of the network on chip by 30%. The total power consumption required to achieve the proposed design is slightly increased by 11%. The proposed design improves Perform-ability range in comparison with conventional schemes while saving energy by 5%. BCH achieves high perform-ability