David V. Overhauser / Jeong-Taek Kong
Digital Timing Macromodeling for VLSI Design Verification
- Springer US
- 2012
- Taschenbuch
- 292 Seiten
- ISBN 9781461359821
Digital Timing Macromodeling for VLSI Design Verification first of all provides an extensive history of the development of simulation techniques. It presents detailed discussion of the various techniques implemented in circuit, timing, fast-timing, switch-level timing, switch-level, and gate-level simulation. It also discusses mixed-mode simulation and interconnection analysis methods. The review in Chapter 2 gives an understanding of the advantages and disadvantages of the many techniques applied in modern digital macromodels. The book also presents a wide variety of techniques for performing nonlinear macromodeling of digital MOS subcircuits which address a large number of shortcomings in existing digital MOS macromodels. Specifically, the techniques address the device model
Mehr
Weniger
zzgl. Versand
in Kürze