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Mikhail Kovalev / Wolfgang J. Paul / Silvia M. Müller
A Pipelined Multi-core MIPS Machine
- Springer International Publishing
- 2014
- Taschenbuch
- 364 Seiten
- ISBN 9783319139050
This monograph is based on the third author's lectures on computer architecture, given in the summer semester 2013 at Saarland University, Germany. It contains a gate level construction of a multi-core machine with pipelined MIPS processor cores and a sequentially consistent shared memory. The book contains the first correctness proofs for both the gate level implementation of a multi-core processor and also of a cache based sequentially consistent shared memory. This opens the way to the formal verification of synthesizable hardware for multi-core processors in the future. Constructions are in a gate level hardware model and thus deterministic. In contrast the reference models against which correctness
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